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| Freescale Semiconductor Data Sheet: Product Preview Document Number: MPC5553 Rev. 0, 06/2006 MPC5553 Microcontroller Data Sheet by: Microcontroller Division This document provides electrical specifications, pin assignments, and package diagrams for the MPC5553 microcontroller device. For functional characteristics, refer to the MPC5553/MPC5554 Microcontroller Reference Manual. Contents 1 2 3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 5 3.3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 EMI (Electromagnetic Interference) Characteristics 9 3.5 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 VRC/POR Electrical Specifications . . . . . . . . . . . . 10 3.7 Power Up/Down Sequencing. . . . . . . . . . . . . . . . . 11 3.8 DC Electrical Specifications. . . . . . . . . . . . . . . . . . 13 3.9 Oscillator & FMPLL Electrical Characteristics . . . . 19 3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 20 3.11 H7Fa Flash Memory Electrical Characteristics . . . 21 3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14 Fast Ethernet AC Timing Specifications . . . . . . . . 45 Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.1 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.2 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . 55 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 1 Overview The MPC5553 microcontroller (MCU) is a member of the MPC5500 family of microcontrollers based on the PowerPCTM Book E architecture. This family of parts contains many new features coupled with high performance CMOS technology to provide substantial reduction of cost per feature and significant performance improvement over the MPC500 family. The host processor core of this device is compatible with the PowerPC Book E architecture. It is 100% user mode compatible (with floating point library) with the classic PowerPC instruction set. The Book E architecture has enhancements that improve the PowerPC architecture's fit in embedded applications. This core also has additional instructions, including digital signal processing (DSP) instructions, beyond the classic 4 5 This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2006. All rights reserved. * Preliminary--Subject to Change Without Notice Overview PowerPC instruction set. This family of parts contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565. The MPC5553 of the MPC5500 family has two levels of memory hierarchy. The fastest accesses are to the 8-kilobyte unified cache. The next level in the hierarchy contains the 64-kilobyte on-chip internal SRAM and 1.5 Mbyte internal Flash memory. Both the internal SRAM and the Flash memory can hold instructions and data. The external bus interface has been designed to support most of the standard memories used with the MPC5xx family. The complex I/O timer functions of the MPC5500 family are performed by an enhanced time processor unit engine (eTPU). The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over the TPU by providing 24-bit timers, double action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU can be programmed using a high-level programming language. The less complex timer functions of the MPC5500 family are performed by the enhanced modular input/output system (eMIOS). The eMIOS' 24 hardware channels are capable of single action, double action, pulse width modulation (PWM), and modulus counter operation. Motor control capabilities include edge-aligned and center-aligned PWM. Off-chip communication is performed by a suite of serial protocols including controller area networks (FlexCANs), enhanced deserial/serial peripheral interfaces (DSPI), and enhanced serial communications interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of timer channels and general-purpose input/output (GPIO) signals. The MCU of the MPC5553 has an on-chip 40-channel enhanced queued dual analog-to-digital converter (eQADC). The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset control are also found in the SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs and external interrupt signal multiplexing. MPC5553 Microcontroller Data Sheet, Rev. 0 2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Ordering Information 2 Ordering Information M PC 5553 M ZP 80 R2 Qualification Status Core Code Device Number Temperature Range Package Identifier Operating Frequency (MHz) Tape and Reel Status Temperature Range M = -40 C to 125 C A = -55 C to 125 C Package Identifier ZP = 416PBGA SnPb VR = 416PBGA Pb-free VF = 208MAPBGA SnPb VM = 208MAPBGA Pb-free ZQ = 324PBGA SnPb VZ = 324PBGA Pb-free Operating Frequency 80 = 80MHz 112 = 112MHz 132 = 132MHz Tape and Reel Status R2 = Tape and Reel (blank) = Trays Qualification Status P = Pre Qualification M = Full Spec Qualified Note: Not all options are available on all devices. Refer to Table 1. Figure 1. MPC5500 Family Part Number Example Table 1. Orderable Part Numbers Freescale Part Number MPC5553MVR132 MPC5553MZP132 MPC5553MVZ132 MPC5553MZQ132 MPC5553MVF132 MPC5553MVM132 MPC5553MVR112 MPC5553MZP112 MPC5553MVZ112 MPC5553MZQ112 MPC5553MVF112 MPC5553MVM112 MPC5553MVR80 MPC5553MZP80 MPC5553MVZ80 MPC5553MZQ80 Description MPC5553 Lead free 416 package MPC5553 Lead 416 package MPC5553 Lead free 324 package MPC5553 Lead 324 package MPC5553 Lead 208 package MPC5553 Lead free 208 package MPC5553 Lead free 416 package MPC5553 Lead 416 package MPC5553 Lead free 324 package MPC5553 Lead 324 package MPC5553 Lead 208 package MPC5553 Lead free 208 package MPC5553 Lead free 416 package MPC5553 Lead 416 package MPC5553 Lead free 324 package MPC5553 Lead 324 package Speed (MHz) 132 132 132 132 132 132 112 112 112 112 112 112 80 80 80 80 Max Speed1 (MHz) (fMAX) 132 132 132 132 132 132 114 114 114 114 114 114 82 82 82 82 Temperature -40 C to 125 C -40 C to 125 C -40 C to 125 C -40 C to 125 C -40 C to 125 C -40 C to 125 C -40 C to 125 C -40 C to 125 C -40 C to 125 C -40 C to 125 C -40 C to 125 C -40 C to 125 C -40 C to 125 C -40 C to 125 C -40 C to 125 C -40 C to 125 C MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 3 Electrical Characteristics Table 1. Orderable Part Numbers (continued) MPC5553MVF80 MPC5553MVM80 1 MPC5553 Lead 208 package MPC5553 Lead free 208 package 80 80 82 82 -40 C to 125 C -40 C to 125 C Speed is the nominal maximum frequency. Max Speed is the maximum speed allowed including any frequency modulation. 80-MHz parts allow for 80 MHz + 2% modulation. However, 132-MHz allows only 128 MHz + 2% FM. 3 Electrical Characteristics This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MCU. 3.1 Maximum Ratings Table 2. Absolute Maximum Ratings1 Num 1 2 3 4 5 6 7 8 9 10 11 12 Characteristic 1.5V Core Supply Voltage 3 Flash Program/Erase Voltage Flash Core Voltage Flash Read Voltage SRAM Standby Voltage Clock Synthesizer Voltage 3.3V I/O Buffer Voltage Voltage Regulator Control Input Voltage Analog Supply Voltage (reference to VSSA) I/O Supply Voltage (Fast I/O Pads) Voltage5 4 4 Symbol VDD VPP VDDF VFLASH VSTBY VDDSYN VDD33 VRC33 VDDA VDDE VDDEH VIN Min - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 -0.3 -0.3 - 0.3 - 0.3 - 0.3 -1.06 -0.37 -1.06 Max2 1.7 6.5 1.7 4.6 1.7 4.6 4.6 4.6 5.5 4.6 6.5 6.58 Unit V V V V V V V V V V V I/O Supply Voltage (Slow/Medium I/O Pads) DC Input VDDEH powered I/O Pads, except eTPUB15 and SINB (DSPI_B_SIN) VDDEH powered I/O Pads (eTPUB15 and SINB) VDDE powered I/O Pads Analog Reference High Voltage (reference to VRL) VSS Differential Voltage VDD Differential Voltage VREF Differential Voltage VRH to VDDA Differential Voltage VRL to VSSA Differential Voltage VDDEH to VDDA Differential Voltage VDDF to VDD Differential Voltage This spec has been moved to Table 9, spec 43a. VSSSYN to VSS Differential Voltage V 6.58 4.69 5.5 0.1 VDD 5.5 5.5 0.3 VDDEH 0.3 V V V V V V V V 13 14 15 16 17 18 19 20 21 22 VRH VSS - VSSA VDD - VDDA VRH - VRL VRH - VDDA VRL - VSSA VDDEH - VDDA VDDF - VDD VSSSYN - VSS - 0.3 - 0.1 - VDDA - 0.3 - 5.5 - 0.3 -VDDA -0.3 -0.1 0.1 V MPC5553 Microcontroller Data Sheet, Rev. 0 4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 2. Absolute Maximum Ratings1 (continued) Num 23 24 25 26 27 28 29 1 Characteristic VRCVSS to VSS Differential Voltage Maximum DC Digital Input Current digital pins)5 10 Symbol VRCVSS - VSS Min -0.1 -2 -3 - 40.0 - 55.0 -- -- Max2 0.1 2 3 150.0 150.0 260.0 3 Unit V mA mA o (per pin, applies to all IMAXD IMAXA TJ TSTG Maximum DC Analog Input Current 11 (per pin, applies to all analog pins) Maximum Operating Temperature Range 12 -- Die Junction Temperature Storage Temperature Range Maximum Solder Temperature Moisture Sensitivity Level 14 13 C C C o o TSDR MSL Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. 3 1.5V +/- 10% for proper operation. This parameter is specified at a maximum junction temperature of 150C. 4 All functional non-supply I/O pins are clamped to VSS and VDDE or VDDEH. 5 AC signal over and undershoot of the input voltages of up to +/- 2.0 volts is permitted for a cumulative duration of 60 hours over the complete lifetime of the device (injection current does not need to be limited for this duration). 6 Internal structures will hold the voltage above -1.0 volt if the injection current limit of 1 mA is met. 7 Internal structures will not clamp to a safe voltage. External protection must be used to ensure that voltage on the pin stays above -0.3 volts. 8 Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDEH supplies, if the maximum injection current specification is met (1 mA for all pins) and VDDEH is within Operating Voltage specifications. 9 Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDE supplies, if the maximum injection current specification is met (1 mA for all pins) and VDDE is within Operating Voltage specifications. 10 Total injection current for all pins (including both digital and analog) must not exceed 25mA. 11 Total injection current for all analog input pins must not exceed 15mA. 12 Lifetime operation at these specification limits is not guaranteed. 13 Solder profile per CDF-AEC-Q100. 14 Moisture sensitivity per JEDEC test method A112. 3.2 Thermal Characteristics Table 3. Thermal Characteristics Value Num 1 Characteristic Junction to Ambient 1, 2 Natural Convection (Single layer board) Junction to Ambient 1, 3 Natural Convection (Four layer board 2s2p) Symbol RJA Unit 208 MAPBGA 324 PBGA 416 PBGA C/W 41 30 29 2 RJA C/W 25 21 21 MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5 Electrical Characteristics Table 3. Thermal Characteristics (continued) Value Num 3 Characteristic Junction to Ambient 1, 3 (@200 ft./min., Single layer board) Junction to Ambient 1, 3 (@200 ft./min., Four layer board 2s2p) Junction to Board 4 (Four layer board 2s2p) Junction to Case 5 Junction to Package Top Natural Convection 6 Symbol RJMA Unit 208 MAPBGA 324 PBGA 416 PBGA C/W 33 24 23 4 RJMA C/W 22 17 18 5 6 7 1 RJB RJC JT C/W C/W C/W 15 7 2 12 8 2 13 9 2 2 3 4 5 6 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 3.2.1 General Notes for Specifications at Maximum Junction Temperature An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJA x PD) where: TA = ambient temperature for the package (oC) RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The supplied thermal resistances are provided based on JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined on the single-layer (1s) board and on the four-layer board with two signal layers and a power and a ground plane (2s2p) clearly demonstrate that the effective thermal resistance of the component is not a constant. It depends on the construction of the application board (number of planes), the effective size of the board which cools the component, how well the component is thermally and electrically connected to the planes, and the power being dissipated by adjacent components. Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal MPC5553 Microcontroller Data Sheet, Rev. 0 6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics performance. When the clearance between through vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the application board has one oz (35 micron nominal thickness) internal planes, the components are well separated, and the overall power dissipation on the board is less than 0.02 W/cm2. The thermal performance of any component depends strongly on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RJB x PD) where: TJ = junction temperature (oC) TB = board temperature at the package perimeter (oC/W) RJB = junction to board thermal resistance (oC/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition, with the component soldered to a board with internal planes. Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RJA = RJC + RCA where: RJA = junction to ambient thermal resistance (oC/W) RJC = junction to case thermal resistance (oC/W) RCA = case to ambient thermal resistance (oC/W) RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7 Electrical Characteristics to the printed circuit board. This model can be used for either hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TT = thermocouple temperature on top of the package (oC) JT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International 805 East Middlefield Rd Mountain View, CA 94043 (415) 964-5111 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. * 1. C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. * 2. G. Kromann, S. Shidore, and S. Addison, "Thermal Modeling of a PBGA for Air-Cooled Applications," Electronic Packaging and Production, pp. 53-58, March 1998. * 3. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling," Proceedings of SemiTherm, San Diego, 1999, pp. 212-220. 3.3 Package The MPC5553 is available in packaged form. Package options are listed in Section 2, "Ordering Information." Refer to Section 4, "Mechanicals," for pinouts and package drawings. MPC5553 Microcontroller Data Sheet, Rev. 0 8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.4 Num 1 2 3 4 5 6 7 1 EMI (Electromagnetic Interference) Characteristics Table 4. EMI Testing Specifications1 Characteristic Scan Range Operating Frequency VDD Operating Voltages VDDSYN, VRC33, VDD33, VFLASH, VDDE Operating Voltages VPP, VDDEH, VDDA Operating Voltages Maximum Amplitude Operating Temperature Min. Value 0.15 -- -- -- -- -- -- Typ. Value -- -- 1.5 3.3 5.0 -- -- Max. Value 1000 132 -- -- -- 142 323 25 o Unit MHz MHz V V V dBuV C EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing is performed on the MPC5554 and applied to MPC5500 family as generic EMI performance data. 2 As measured with "single-chip" EMI program. 3 As measured with "expanded" EMI program. 3.5 ESD Characteristics Table 5. ESD Ratings1, 2 Characteristic Symbol Value 2000 R1 C 1500 100 500 (all pins) 750 (corner pins) V Unit V Ohm pF ESD for Human Body Model (HBM) HBM Circuit Description ESD for Field Induced Charge Model (FDCM) Number of Pulses per pin: Positive Pulses (HBM) Negative Pulses (HBM) Interval of Pulses 1 2 -- -- -- 1 1 1 -- -- second All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9 Electrical Characteristics 3.6 VRC/POR Electrical Specifications Table 6. VRC/POR Electrical Specifications Num 1 2 3 4 5 6 7 Characteristic 1.5V (VDD) POR Negated (Ramp Up) 1.5V (VDD) POR Asserted (Ramp Down) 3.3V (VDDSYN) POR Negated (Ramp Up) 3.3V (VDDSYN) POR Asserted (Ramp Down) RESET Pin Supply (VDDEH6) POR Negated (Ramp Up) RESET Pin Supply (VDDEH6) POR Asserted (Ramp Down) VRC33 voltage before regulator controller allows the pass transistor to start turning on VRC33 voltage when regulator controller allows the pass transistor to completely turn on1, 2 VRC33 voltage above which the regulator controller will keep the 1.5V supply in regulation3, 4 Current which can be sourced by VRCCTL - 40C 25C 150C (Tj) Symbol V_POR15 V_POR33 V_POR5 V_TRANS_ START V_TRANS_ON V_VRC33REG I_VRCCTL5 Min 1.1 1.1 2.0 2.0 2.0 2.0 1.0 2.0 3.0 Max 1.35 1.35 2.85 2.85 2.85 2.85 2.0 2.85 -- Units V V V V V V mA 11.0 9.0 7.5 VDD33_LAG -- -- -- -- 1.0 mA mA mA V 8 Voltage differential during power up that VDD33 can lag VDDSYN or VDDEH6 before VDDSYN and VDDEH6 reach V_POR33 and V_POR5 minimums respectively Absolute value of Slew Rate on power supply pins Required Gain: Idd / I_VRCCTL (@vdd = 1.35v, fsys = 132MHz)4, 6 - 40C 25C 150C (Tj) 9 10 -- BETA7 55.08 58.0 8 50 V/ms -- -- 500 -- -- -- 70.08 1 2 3 4 5 6 7 8 User must be able to supply full operating current for the 1.5V supply when the 3.3V supply reaches this range. Current limit may be reached during ramp up and should not be treated as short circuit current. At peak current for device. Assumes that the Freescale recommended board requirements and transistor recommendations are met. Board signal traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass transistor to the VDD package signals should have a maximum of 100 nH inductance and minimal resistance (<1 ohm). VRCCTL should have a nominal 1F phase compensation capacitor to ground. VDD should have a 20 F (nominal) bulk capacitor (> 4 F over all conditions, including lifetime). High frequency bypass capacitors consisting of eight 0.01 F, two 0.1 F, and one 1 F capacitors should be place around the package on the VDD supply signals. I_VRCCTL measured at the following conditions: VDD=1.35V, VRC33=3.1V, V_VRCCTL=2.2V. Values are based on IDD from high use applications as explained in the IDD Electrical Specification. BETA is measured on a per part basis and is calculated as IDD / I_VRCCTL and represents the worst case external transistor BETA. Preliminary value. Final specification pending characterization. MPC5553 Microcontroller Data Sheet, Rev. 0 10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.7 Power Up/Down Sequencing Power sequencing between the 1.5-V power supply and VDDSYN or the RESET power supplies is required if the user provides an external 1.5-V power supply and ties VRC33 to ground. To avoid this power sequencing requirement, power up VRC33 within the specified operating range, even if not using the on-chip voltage regulator controller. Refer to Section 3.7.1, "Power Up Sequence (If VRC33 Grounded)" and Section 3.7.2, "Power Down Sequence (If VRC33 Grounded)." Another power sequencing requirement is that VDD33 must be of sufficient voltage before POR negates, so that the values on certain pins are treated as 1s when POR does negate. Refer to Section 3.7.3, "Input Value of Pins During POR Dependent on VDD33." Although there is no power sequencing required between VRC33 and VDDSYN during power up, for the VRC stage turn-on to operate within specification, VRC33 must not lead VDDSYN by more than 600 mV or lag by more than 100 mV. Higher spikes in the emitter current of the pass transistor will occur if VRC33 leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance. Furthermore, when all of the PORs negate, the system clock will start to toggle, adding another large increase of the current consumption from VRC33. If VRC33 lags VDDSYN by more than 100 mV, this increased current consumption can drop VDD low enough to assert the 1.5-V POR again. Oscillations are even possible because when the 1.5-V POR asserts, the system clock stops, causing the voltage on VDD to rise until the 1.5-V POR negates again. Any oscillations stop when VRC33 is powered sufficiently. When powering down, VRC33 and VDDSYN do not have a delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. When not powering up or down, VRC33 and VDDSYN do not have a delta requirement to each other for the VRC to operate within specification. Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type), and Table 8 for all pins with pad type pad_mh (medium type) and pad_sh (slow type). Table 7. Power Sequence Pin States (Fast Pads) VDDE LOW VDDE VDDE VDDE VDD33 X LOW VDD33 VDD33 VDD X X LOW VDD pad_fc (Fast) Output Driver State Low High High Impedance Functional POR asserted. No POR asserted Comment Functional I/O pins are clamped to VSS and VDDE MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11 Electrical Characteristics Table 8. Power Sequence Pin States (Medium and Slow Pads) VDDEH LOW VDDEH VDDEH VDD X LOW VDD pad_mh/pad_sh (Medium and Slow) Output Driver Low High Impedance Functional Comment Functional I/O pins are clamped to VSS and VDDEH POR asserted No POR asserted 3.7.1 Power Up Sequence (If VRC33 Grounded) In this case, the 1.5-V VDD supply must rise to 1.35-V before the 3.3-V VDDSYN and the RESET power supplies rises above 2.0 V. This ensures that digital logic in the PLL on the 1.5-V supply will not begin to operate below the specified operation range lower limit of 1.35 V. Since the internal 1.5-V POR is disabled, the internal 3.3-V POR or the RESET power POR must be depended on to hold the device in reset. Since they may negate as low as 2.0 V, it is necessary for VDD to be within spec before the 3.3-V POR and the RESET POR negate. VDDSYN and RESET Power VDD 2.0V 1.35V VDD must reach 1.35V before VDDSYN and the RESET power reach 2.0V Figure 2. Power Up Sequence if VRC33 Grounded 3.7.2 Power Down Sequence (If VRC33 Grounded) In this case, the only requirement is that if VDD falls below its operating range, VDDSYN or the RESET power must fall below 2.0 V before VDD is allowed to rise back into its operating range. This ensures that digital 1.5-V logic that is only reset by ORed_POR, which may have been affected by the 1.5V supply falling below spec, is reset properly. 3.7.3 Input Value of Pins During POR Dependent on VDD33 In order to avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not treated as 1s when POR negates, VDD33 must not lag VDDSYN and the RESET pin power (VDDEH6) when powering the device by more than the VDD33 lag specification in Table 6. VDD33 individually can lag either VDDSYN or the RESET pin power (VDDEH6) by more than the VDD33 lag specification. VDD33 can lag one of the VDDSYN or VDDEH6 supplies, but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification only applies during power up. VDD33 has no lead or lag requirements when powering down. MPC5553 Microcontroller Data Sheet, Rev. 0 12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.8 DC Electrical Specifications Table 9. DC Electrical Specifications Num 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Characteristic Core Supply Voltage (average DC RMS voltage) I/O Supply Voltage (Fast I/O) I/O Supply Voltage (Slow/Medium I/O) 3.3V I/O Buffer Voltage Voltage Regulator Control Input Voltage Analog Supply Voltage 1 Symbol VDD VDDE VDDEH VDD33 VRC33 VDDA VPP VFLASH VSTBY VDDSYN VIH_F VIL_F VIH_S VIL_S VHYS_F VHYS_S VINDC VOH_F VOH_S VOL_F VOL_S CL Min 1.35 1.62 3.0 3.0 3.0 4.5 4.5 3.0 0.8 3.0 0.65 * VDDE VSS - 0.3 0.65 * VDDEH VSS - 0.3 Max 1.65 3.6 5.25 3.6 3.6 5.25 5.25 3.6 1.2 3.6 VDDE + 0.3 0.35 * VDDE VDDEH + 0.3 0.35 * VDDEH Unit V V V V V V V V V V V V V V V V V V V V V Flash Programming Voltage2 Flash Read Voltage SRAM Standby Voltage3 Clock Synthesizer Operating Voltage Fast I/O Input High Voltage Fast I/O Input Low Voltage Medium/Slow I/O Input High Voltage Medium/Slow I/O Input Low Voltage Fast I/O Input Hysteresis Medium/Slow I/O Input Hysteresis Analog Input Voltage Fast I/O Output High Voltage (IOH_F = -2.0mA) Slow/Medium I/O Output High Voltage (IOH_S = -2.0mA) Fast I/O Output Low Voltage (IOL_F = 2.0mA) Slow/Medium I/O Output Low Voltage (IOL_S = 2.0mA) Load Capacitance (Fast I/O)4 DSC(SIU_PCR[8:9]) = 0b00 DSC(SIU_PCR[8:9]) = 0b01 DSC(SIU_PCR[8:9]) = 0b10 DSC(SIU_PCR[8:9]) = 0b11 Input Capacitance (Digital Pins) Input Capacitance (Analog Pins) 0.1 * VDDE 0.1 * VDDEH VSSA - 0.3 0.8 * VDDE 0.8 * VDDEH -- -- VDDA + 0.3 -- -- 0.2 * VDDE 0.2 * VDDEH 10 20 30 50 7 10 -- -- -- CIN CIN_A -- -- pF pF pF pF pF pF 24 25 MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13 Electrical Characteristics Table 9. DC Electrical Specifications (continued) Num 26 Characteristic Input Capacitance (Shared digital and analog pins AN12_MA0_SDS, AN12_MA1_SDO, AN14_MA2_SDI, and AN15_FCK) Symbol CIN_M Min -- Max 12 Unit pF 27a Operating Current5 1.5V Supplies @ 132MHz: VDD (including VDDF max current)6, 7 @1.65V Typical Use VDD (including VDDF max current)6, 7 @1.35V Typical Use VDD (including VDDF max current) 7, 8 @1.65V High Use VDD (including VDDF max current)7, 8@1.35V High Use 27b Operating Current 51.5V Supplies @ 114MHz: VDD (including VDDF max current)6, 7@1.65V Typical Use VDD (including VDDF max current)6, 7@1.35V Typical Use VDD (including VDDF max current)7, 8 @1.65V High Use VDD (including VDDF max current)7, 8 @1.35V High Use 27c Operating Current5 1.5V Supplies @ 82MHz: VDD (including VDDF max current)6, 7 @1.65V Typical Use VDD (including VDDF max current)6, 7 @1.35V Typical Use VDD (including VDDF max current)7, 8 @1.65V High Use VDD (including VDDF max current)7, 8 @1.35V High Use 27d IDDSTBY @ 25C VSTBY @ 0.8V VSTBY @ 1.0V VSTBY @ 1.2V IDDSTBY @ 60C VSTBY @ 0.8V VSTBY @ 1.0V VSTBY @ 1.2V IDDSTBY @ 150C (Tj) VSTBY @ 0.8V VSTBY @ 1.0V VSTBY @ 1.2V 28 Operating Current 3.3V Supplies @ 132MHz: VDD3310 IDD33 -- 2 + values derived from procedure of Footnote 10 IDD IDD IDD IDD -- -- -- -- 5509 4509 6009 4909 mA mA mA mA IDD IDD IDD IDD -- -- -- -- 4609 3809 5209 4209 mA mA mA mA IDD IDD IDD IDD -- -- -- -- 3509 2909 4009 3309 mA mA mA mA IDDSTBY IDDSTBY IDDSTBY -- -- -- 20 30 50 A A A A A A A A A IDDSTBY IDDSTBY IDDSTBY -- -- -- 70 100 200 IDDSTBY IDDSTBY IDDSTBY -- -- -- 1200 1500 2000 mA VFLASH VDDSYN IVFLASH IDDSYN -- -- 10 15 mA mA MPC5553 Microcontroller Data Sheet, Rev. 0 14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 9. DC Electrical Specifications (continued) Num 29 Characteristic Operating Current 5.0V Supplies @ 132MHz (12MHz ADCLK): VDDA (VDDA0 + VDDA1) Analog Reference Supply Current (VRH, VRL) VPP 30 Operating Current VDDE11 Supplies: VDDEH1 VDDE2 VDDE3 VDDEH4 VDDE5 VDDEH6 VDDE7 VDDEH8 VDDEH9 Fast I/O Weak Pull Up Current12 1.62V - 1.98V 2.25V - 2.75V 3.0V - 3.6V Fast I/O Weak Pull Down Current12 1.62V - 1.98V 2.25V - 2.75V 3.0V - 3.6V 32 Slow/Medium I/O Weak Pull Up/Down Current13 3.0V - 3.6V 4.5V - 5.5V I/O Input Leakage Current14 DC Injection Current (per pin) Analog Input Current, Channel Off15 IACT_S 10 20 IINACT_D IIC IINACT_A IINACT_AD VSS - VSSA VRL VRL - VSSA VRH VRH - VRL VSSSYN - VSS VRCVSS - VSS VDDF - VDD - 2.5 - 2.0 -150 - 2.5 - 100 VSSA - 0.1 -100 VDDA - 0.1 4.5 -50 -50 -100 150 170 2.5 2.0 150 2.5 100 VSSA + 0.1 100 VDDA + 0.1 5.25 50 50 100 IDDA IREF IPP -- -- -- -- 20.0 1.0 25 mA mA mA Symbol Min Max Unit IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 IDD8 IDD9 IACT_F -- -- -- -- -- -- -- -- -- 10 20 20 10 20 20 See Footnote 11 mA mA mA mA mA mA mA mA mA A A A A A A A A A mA nA A mV V mV V V mV mV mV 31 110 130 170 100 130 170 33 34 35 35a Analog Input Current, Shared Analog/Digital pins (AN12, AN13, AN14, AN15) 36 37 38 39 40 41 42 43 VSS Differential Voltage16 Analog Reference Low Voltage VRL Differential Voltage Analog Reference High Voltage VREF Differential Voltage VSSSYN to VSS Differential Voltage VRCVSS to VSS Differential Voltage VDDF to VDD Differential Voltage2 MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15 Electrical Characteristics Table 9. DC Electrical Specifications (continued) Num Characteristic Symbol VRC33 - VDDSYN VIDIFF TA (TL to TH) -- Min -0.1 - 2.5 - 40.0 -- Max 0.117 2.5 125.0 50 Unit V V 43a VRC33 to VDDSYN Differential Voltage 44 45 46 1 2 Analog Input Differential Signal Range (with common mode 2.5V) Operating Temperature Range -- Ambient (Packaged) Slew rate on power supply pins C V/ms | VDDA0-VDDA1 | must be < 0.1V VPP can drop to 3.0 volts during read operations. 3 During standby operation. If standby operation is not required, VSTBY can be connected to ground. 4 Applies to CLKOUT, external bus pins, and Nexus pins. 5 Maximum average RMS DC current. 6 Average current measured on Automotive benchmark. 7 Peak currents may be higher on specialized code. 8 High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache (0% miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from SRAM to SRAM. Higher currents could be seen if an "idle" loop that crosses cache lines is run from cache. Code should be written to avoid this condition. 9 Preliminary. Final specification pending characterization. 10 Power requirements for the VDD33 supply are dependent on the frequency of operation and load of all I/O pins, and the voltages on the I/O segments. See Table 11 for values to calculate power dissipation for specific operation. 11 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. See Table 10 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment. 12 Absolute value of current, measured at V and V . IL IH 13 Absolute value of current, measured at V and V . IL IH 14 Weak pull up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh. 15 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae. 16 VSSA refers to both VSSA0 and VSSA1. | VSSA0-VSSA1 | must be < 0.1V 17 Up to 0.6 volts during power up and power down. 3.8.1 I/O Pad Current Specifications The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 10. MPC5553 Microcontroller Data Sheet, Rev. 0 16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 10. I/O Pad Average DC Current1 Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 Pad Type Slow Symbol IDRV_SH Frequency (MHz) 25 10 2 2 Load2 (pF) 50 50 50 200 50 50 50 200 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 Voltage (V) 5.25 5.25 5.25 5.25 5.25 5.25 5.25 5.25 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 Drive Select / Slew Rate Control 11 01 00 00 11 01 00 00 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Current (mA) 8.0 3.2 0.7 2.4 17.3 6.5 1.1 3.9 2.8 5.2 8.5 11.0 1.6 2.9 4.2 6.7 2.4 4.4 7.2 9.3 1.3 2.5 3.5 5.7 1.7 3.1 5.1 6.6 1.0 1.8 2.5 4.0 Medium IDRV_MH 50 20 3.33 3.33 Fast IDRV_FC 66 66 66 66 66 66 66 66 56 56 56 56 56 56 56 56 40 40 40 40 40 40 40 40 These values are estimated from simulation and are not tested. Currents apply to output pins only. All loads are lumped. 3.8.2 I/O Pad VDD33 Current Specifications The power consumption of the VDD33 supply dependents on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The output pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all fast (pad_fc) pins. The input pin VDD33 current can be calculated from Table 11 based on the voltage, MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17 Electrical Characteristics frequency, and load on all pad_sh and pad_sh pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 11. Table 11. VDD33 Pad Average DC Current1 Num Pad Type Symbol Frequency (MHz) Load2 (pF) Inputs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 VDD33 (V) VDDE (V) Drive Select Current (mA) Slow Medium Fast I33_SH I33_MH I33_FC 66 66 66 66 66 66 66 66 66 66 56 56 56 56 56 56 56 56 40 40 40 40 40 40 40 40 0.5 0.5 Outputs 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 5.5 5.5 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 NA NA 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 0.003 0.003 0.35 0.53 0.62 0.79 0.35 0.44 0.53 0.7 0.30 0.45 0.52 0.67 0.30 0.37 0.45 0.60 0.21 0.31 0.37 0.48 0.21 0.27 0.32 0.42 These values are estimated from simulation and not tested. Currents apply to output pins only for the fast pads and to input pins only for the slow and medium pads. 2 All loads are lumped. MPC5553 Microcontroller Data Sheet, Rev. 0 18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.9 Oscillator & FMPLL Electrical Characteristics Table 12. HiP7 FMPLL Electrical Specifications (VDDSYN = 3.0V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH) Num 1 Characteristic PLL Reference Frequency Range: Crystal reference External reference Dual Controller (1:1 mode) System Frequency 1 System Clock Period Loss of Reference Frequency 3 4 Symbol Min. Value 8 8 24 fico(min) / 2RFD -- 100 7.4 Vxtal + 0.4v ((VDDE5/2) + 0.4v) Max. Value 20 20 fsys/2 fMAX 2 1 / fsys 1000 17.5 -- -- Unit MHz fref_crystal fref_ext fref_1:1 fsys tCYC fLOR fSCM VIHEXT VIHEXT 2 3 4 5 6 MHz ns kHz MHz V V Self Clocked Mode (SCM) Frequency EXTAL Input High Voltage Crystal Mode 5 All other modes (Dual Controller (1:1), Bypass, External Reference) 7 EXTAL Input Low Voltage Crystal Mode 6 All other modes (Dual Controller (1:1), Bypass, External Reference) 8 9 10 11 12 13 14 15 16 17 18 19 XTAL Current 7 Total On-chip stray capacitance on XTAL Total On-chip stray capacitance on EXTAL Crystal manufacturer's recommended capacitive load Discrete load capacitance to be connected to EXTAL Discrete load capacitance to be connected to XTAL PLL Lock Time9 Dual Controller (1:1) Clock Skew (between CLKOUT and EXTAL) 10, 11 Duty Cycle of reference Frequency un-LOCK Range Frequency LOCK Range CLKOUT Period Jitter, Measured at fSYS Max Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter (Averaged over 2 ms interval) 12, 13 VILEXT VILEXT IXTAL CS_XTAL CS_EXTAL CL CL_EXTAL CL_XTAL tlpll tskew tdc fUL fLCK Cjitter -- -- 0.8 -- -- See crystal specification -- -- -- -2 40 - 4.0 - 2.0 Vxtal - 0.4v ((VDDE5/2) - 0.4v) 3 1.5 1.5 See crystal specification 2*CL - CS_EXTAL - CPCB_EXTAL8 2*CL - CS_XTAL - CPCB_XTAL8 750 2 60 4.0 2.0 V V mA pF pF pF pF pF s ns % % fsys % fsys % fclkout -- -- 5.0 .01 MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19 Electrical Characteristics Table 12. HiP7 FMPLL Electrical Specifications (continued) (VDDSYN = 3.0V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH) Num 20 21 22 1 2 Characteristic Frequency Modulation Range Limit 14 (fsysMax must not be exceeded) ICO Frequency. fico=[fref*(MFD+4)]/(PREDIV+1)15 Predivider Output Frequency (to PLL) Symbol Cmod fico fPREDIV Min. Value 0.8 48 4 Max. Value 2.4 fsys fMAX Unit %fsys MHz MHz All internal registers retain data at 0 Hz. Up to the maximum frequency rating of the device (see Table 1). 3 "Loss of Reference Frequency" is the reference frequency detected internally, which transitions the PLL into self clocked mode. 4 Self clocked mode (SCM) frequency is the frequency that the PLL operates at when the reference frequency falls below f LOR. This frequency is measured on the CLKOUT pin with the divider set to divide-by-2 of the system clock. NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed. 5 This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case, Vextal - Vxtal >= 400mV criteria has to be met for oscillator's comparator to produce output clock. 6 This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case, Vxtal - Vextal >= 400mV criteria has to be met for oscillator's comparator to produce output clock. 7I xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. 8C PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively 9 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time will also include the crystal startup time. 10 PLL is operating in 1:1 PLL mode. 11 VDDE = 3.0 to 3.6V 12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . sys Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage for a given interval. CLKOUT divider set to divide-by-2. 13 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of jitter + Cmod. 14 Modulation depth selected must not result in f sys value greater than the fsys maximum specified value. 15 f RFD) sys = fico / (2 3.10 Num 1 2 eQADC Electrical Characteristics Table 13. eQADC Conversion Specifications (Operating) Characteristic ADC Clock (ADCLK) Frequency1 Conversion Cycles Differential Single Ended Stop Mode Recovery Time2 Resolution3 INL: 6 MHz ADC Clock INL: 12 MHz ADC Clock Symbol FADCLK CC 13+2 (or 15) 14+2 (or 16) TSR -- INL6 INL12 10 1.25 -4 -8 13+128 (or 141) 14+128 (or 142) -- -- 4 8 Min 1 Max 12 Unit MHz ADCLK cycles s mV Counts3 Counts 3 4 5 6 MPC5553 Microcontroller Data Sheet, Rev. 0 20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 13. eQADC Conversion Specifications (Operating) (continued) Num 7 8 9 10 11 12 Characteristic DNL: 6 MHz ADC Clock DNL: 12 MHz ADC Clock Offset Error with Calibration Full Scale Gain Error with Calibration Disruptive Input Injection Current 7, 8, 9, 10 Symbol DNL6 DNL12 OFFWC GAINWC IINJ EINJ Min -3 4 -6 -4 -8 4 5 6 Max 34 6 4 8 4 5 6 Unit Counts Counts Counts Counts mA Counts -1 -4 1 4 Incremental Error due to injection current. All channels have same 10k < Rs <100k Channel under test has Rs=10k, IINJ=IINJMAX,IINJMIN Total Unadjusted Error for single ended conversions with calibration11, 12, 13, 14, 15 13 1 TUE -4 4 Counts Conversion characteristics vary with FADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The maximum value is based on 800KS/s and the minimum value is based on 20MHz oscillator clock frequency divided by a maximum 16 factor. 2 Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that the ADC is ready to perform conversions. 3 At VRH - VRL = 5.12 V, one lsb = 1.25 mV = one count 4 Guaranteed 10-bit monotonicity 5 The absolute value of the offset error without calibration 100 counts. 6 The absolute value of the full scale gain error without calibration 120 counts. 7 Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater than VRH and 0x000 for values less than VRL. This assumes that VRH VDDA and VRL VSSA due to the presence of the sample amplifier. Other channels are not affected by non-disruptive conditions. 8 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5V and VNEGCLAMP = - 0.3 V, then use the larger of the calculated values. 10 Condition applies to two adjacent pads on the internal pad. 11 The TUE specification will always be better than the sum of the INL, DNL, offset, and gain errors due to canceling errors. 12 TUE does not apply to differential conversions. 13 Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: -16 counts < TUE < 16 counts. 14 TUE includes all internal device error such as internal reference variation (75% Ref, 25% Ref) 15 Depending on the customer input impedance, the Analog Input Leakage current (DC Electrical specification 35a) may affect the actual TUE measured on analog channels AN12, AN13, AN14, AN15. 3.11 Num 3 4 7 9 H7Fa Flash Memory Electrical Characteristics Table 14. Flash Program and Erase Specifications1 Characteristic Double Word (64 bits) Program Time4 Page Program Time4 Symbol Tdwprogram Tpprogram T16kpperase T48kpperase Min -- -- -- -- Typ 10 22 265 340 Initial Max2 -- 445 400 400 Max3 500 500 5000 5000 Unit s s ms ms 16 Kbyte Block Pre-program and Erase Time 48 Kbyte Block Pre-program and Erase Time MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21 Electrical Characteristics Table 14. Flash Program and Erase Specifications1 (continued) Num 10 8 11 1 2 3 4 5 6 Characteristic 64 Kbyte Block Pre-program and Erase Time 128 Kbyte Block Pre-program and Erase Time Minimum operating frequency for program and erase operations6 Symbol T64kpperase T128kpperase -- Min -- -- 25 Typ 400 500 -- Initial Max2 500 1250 -- Max3 5000 15,000 -- Unit ms ms MHz Typical program and erase times assume nominal supply values and operation at 25 oC. Initial factory condition: 100 program/erase cycles, 25 oC, typical supply voltage, 80MHz minimum system frequency. The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized but not guaranteed. Actual hardware programming times. This does not include software overhead. Page size is 256 bits (8 words). Read frequency of the flash can be up to the maximum operating frequency of the device. There is no minimum read frequency condition. Table 15. Flash EEPROM Module Life (Full Temperature Range) Num 1a 1b 2 Characteristic Number of Program/Erase cycles per block for 16 Kbyte, 48 Kbyte, and 64 Kbyte blocks over the operating temperature range (TJ) Number of Program/Erase cycles per block for 128 Kbyte blocks over the operating temperature range (TJ) Data retention Blocks with 0 - 1,000 P/E cycles Blocks with 1,001 - 100,000 P/E cycles Symbol P/E P/E Retention 20 5 Min 100,000 10,000 Typical1 -- Unit cycles 100,000 cycles -- years 1 Typical endurance is evaluated at 25C. Product qualification is performed to the minimum specification. For additional information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619 "Typical Endurance for Nonvolatile Memory." Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device Reference Manual for definitions of these bit-fields. Table 16. FLASH_BIU Settings vs. Frequency of Operation Maximum Frequency (MHz) up to and including 82 MHz1 APC 0b001 RWSC 0b001 WWSC 0b01 DPFEN 0b00, 0b01, or 0b112 0b00, 0b01, or 0b112 0b00, 0b01, or 0b112 0b00 IPFEN 0b00, 0b01, or 0b112 0b00, 0b01, or 0b112 0b00, 0b01, or 0b112 0b00 PFLIM 0b0000b1103 0b0000b1103 0b0000b1103 0b000 BFEN 0b0, 0b14 up to and including 102 MHz5 0b001 0b010 0b01 0b0, 0b14 up to and including132 MHz6 0b010 0b011 0b01 0b0, 0b14 Default Setting after Reset 1 0b111 0b111 0b11 0b0 This setting allows for 80 MHz system clock with 2% frequency modulation. MPC5553 Microcontroller Data Sheet, Rev. 0 22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 2 3 For maximum flash performance, this should be set to 0b11. For maximum flash performance, this should be set to 0b110. 4 For maximum flash performance, this should be set to 0b1. 5 This setting allows for 100 MHz system clock with 2% frequency modulation. 6 This setting allows for 128 MHz system clock with 2% frequency modulation. 3.12 3.12.1 AC Specifications Pad AC Specifications Table 17. Pad AC Specifications (VDDEH = 5.0V, VDDE = 1.8V)1 Out Delay2, 3, 4 (ns) 26 82 01 75 137 00 377 476 Rise/Fall4, 5 (ns) 15 60 40 80 200 260 8 30 15 35 100 125 2.7 2.5 2.4 2.3 -- -- 7500 9000 Load Drive (pF) 50 200 50 200 50 200 50 200 50 200 50 200 10 20 30 50 50 50 Num 1 Pad Slow High Voltage (SH) SRC/DSC 11 2 Medium High Voltage (MH) 11 16 43 01 34 61 00 192 239 3 Fast 00 01 10 11 3.1 4 5 1 Pull Up/Down (3.6V max) Pull Up/Down (5.5V max) -- -- 2 3 4 5 These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDE = 1.62V to 1.98V, VDDEH = 4.5V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH. This parameter is supplied for reference and is not guaranteed by design and not tested. Out delay is shown in Figure 3. Add a maximum of one system clock to the output delay for delay with respect to system clock. Delay and rise/fall are measured to 20% or 80% of the respective signal. This parameter is guaranteed by characterization before qualification rather than 100% tested. MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23 Electrical Characteristics Table 18. De-rated Pad AC Specifications (VDDEH = 3.3V, VDDE = 3.3V)1 Num 1 Pad Slow High Voltage (SH) SRC/DSC 11 Out Delay2, 3, 4 (ns) 39 120 01 101 188 00 507 597 2 Medium High Voltage (MH) 11 23 64 01 50 90 00 261 305 3 Fast 00 01 10 11 4 5 1 Rise/Fall3, 5 (ns) 23 87 52 111 248 312 12 44 22 50 123 156 2.4 2.2 2.1 2.1 Load Drive (pF) 50 200 50 200 50 200 50 200 50 200 50 200 10 20 30 50 50 50 3.2 Pull Up/Down (3.6V max) Pull Up/Down (5.5V max) -- -- -- -- 7500 9500 2 3 4 5 These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDE = 3.0V to 3.6V, VDDEH = 3.0V to 3.6V, VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH. This parameter is supplied for reference and is not guaranteed by design and not tested. Delay and rise/fall are measured to 20% or 80% of the respective signal. Out delay is shown in Figure 3. Add a maximum of one system clock to the output delay for delay with respect to system clock. This parameter is guaranteed by characterization before qualification rather than 100% tested. MPC5553 Microcontroller Data Sheet, Rev. 0 24 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics VDD/2 Pad Internal Data Input Signal Rising Edge Out Delay Falling Edge Out Delay VOH Pad Output VOL Figure 3. Pad Output Delay 3.13 3.13.1 Num 1 2 3 4 1 AC Timing Reset and Configuration Pin Timing Table 19. Reset and Configuration Pin Timing1 Characteristic RESET Pulse Width RESET Glitch Detect Pulse Width PLLCFG, BOOTCFG, WKPCFG, RSTCFG Setup Time to RSTOUT Valid PLLCFG, BOOTCFG, WKPCFG, RSTCFG Hold Time from RSTOUT Valid Symbol tRPW tGPW tRCSU tRCH Min 10 2 10 0 Max -- -- -- -- Unit tCYC tCYC tCYC tCYC Reset timing specified at FSYS = 132MHz, VDDEH = 3.0V to 5.25V, VDD = 1.35V to 1.65V, TA = TL to TH. MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25 Electrical Characteristics 2 RESET 1 RSTOUT 3 PLLCFG BOOTCFG RSTCFG WKPCFG 4 Figure 4. Reset and Configuration Pin Timing 3.13.2 Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 IEEE 1149.1 Interface Timing Table 20. JTAG Pin AC Electrical Characteristics1 Characteristic Symbol tJCYC tJDC tTCKRISE tTMSS, tTDIS tTMSH, tTDIH tTDOV tTDOI tTDOHZ tJCMPPW tJCMPS tBSDV tBSDVZ tBSDHZ tBSDST tBSDHT Min 100 40 -- 5 25 -- 0 -- 100 40 -- -- -- 50 50 Max -- 60 3 -- -- 20 -- 20 -- -- 50 50 50 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TCK Cycle Time TCK Clock Pulse Width (Measured at VDDE/2) TCK Rise and Fall Times (40% - 70%) TMS, TDI Data Setup Time TMS, TDI Data Hold Time TCK Low to TDO Data Valid TCK Low to TDO Data Invalid TCK Low to TDO High Impedance JCOMP Assertion Time JCOMP Setup Time to TCK Low TCK Falling Edge to Output Valid TCK Falling Edge to Output Valid out of High Impedance TCK Falling Edge to Output High Impedance Boundary Scan Input Valid to TCK Rising Edge TCK Rising Edge to Boundary Scan Input Invalid These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 1.35V to 1.65V, VDDE = 3.0V to 3.6V, VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH, and CL = 30pF with DSC = 0b10, SRC = 0b11. See Table 21 for functional specifications. MPC5553 Microcontroller Data Sheet, Rev. 0 26 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics TCK 2 3 2 1 3 Figure 5. JTAG Test Clock Input Timing TCK 4 5 TMS, TDI 6 7 8 TDO Figure 6. JTAG Test Access Port Timing MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27 Electrical Characteristics TCK 10 JCOMP 9 Figure 7. JTAG JCOMP Timing MPC5553 Microcontroller Data Sheet, Rev. 0 28 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics TCK 11 13 Output Signals 12 Output Signals 14 15 Input Signals Figure 8. JTAG Boundary Scan Timing MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29 Electrical Characteristics 3.13.3 Num 1 2 3 4 5 6 7 8 9 10 11 12 Nexus Timing Table 21. Nexus Debug Port Timing1 Characteristic Symbol tMCYC tMDC 3 3 Min 12 40 -1.5 -1.5 -1.5 4.0 1 4 4 Max 8 60 3.0 3.0 3.0 -- Unit tCYC % ns ns ns tTCYC tMCYC tCYC % ns ns MCKO Cycle Time MCKO Duty Cycle MCKO Low to MDO Data Valid tMDOV tMSEOV tEVTOV tEVTIPW tEVTOPW tTCYC tTDC tNTDIS, tNTMSS tNTDIH, tNTMSH tJOV MCKO Low to MSEO Data Valid MCKO Low to EVTO Data Valid EVTI Pulse Width EVTO Pulse Width TCK Cycle Time TCK Duty Cycle TDI, TMS Data Setup Time TDI, TMS Data Hold Time TCK Low to TDO Data Valid VDDE = 2.25 to 3.0 volts VDDE = 3.0 to 3.6 volts MCKO5 3 -- 60 -- -- 40 8 5 0 0 -- -- 12 9 -- ns ns -- 13 1 RDY Valid to 2 3 4 5 JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.35V to 1.65V, VDDE = 2.25V to 3.6V, VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH, and CL = 30pF with DSC = 0b10. The Nexus AUX port can only run up to 82MHz. The NPC_PCR[MCKO_DIV] must be set to divide by 2 if the system frequency is above 82MHz MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. The maximum frequency must be limited to approximately 16 MHz (VDDE= 2.25 to 3.0 volts) or 22 MHz (VDDE= 3.0 to 3.6 volts) to meet the timing specification for tJOV of 0.2 x tJCYC as outlined in the IEEE-ISTO 5001-2003 specification. The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly. 1 2 MCKO 4 5 MDO MSEO EVTO 3 Output Data Valid Figure 9. Nexus Output Timing MPC5553 Microcontroller Data Sheet, Rev. 0 30 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics TCK 10 11 TMS, TDI 12 TDO Figure 10. Nexus TDI, TMS, TDO Timing MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31 Electrical Characteristics 3.13.4 External Bus Interface (EBI) Timing Table 22. Bus Operation Timing1 40 MHz (ext. bus)2 Min Max -- 56 MHz (ext. bus)2 Min 17.9 Max -- 66 MHz (ext. bus)2 Min 15.2 Max -- ns Signals are measured at 50% VDDE. # Characteristic/Description Symbol Unit Notes 1 CLKOUT Period TC 25.0 2 3 4 5 CLKOUT duty cycle CLKOUT rise time CLKOUT fall time CLKOUT Positive Edge to Output Signal Invalid or High Z (Hold Time) ADDR[8:31] BDIP BG4 BR5 CS[0:3] DATA[0:31] OE RD_WR TA TEA TS TSIZ[0:1] WE[0:3]/BE[0:3] tCDC tCRT tCFT tCOH 45% -- -- 1.06/ 1.5 55% --3 --3 -- 45% -- -- 1.06/ 1.5 55% --3 --3 -- 45% -- -- 1.06/ 1.5 55% --3 --3 -- TC ns ns ns Hold time selectable via SIU_ECCR[EBTS] bit: EBTS=0/EBTS=1 6 CLKOUT Posedge to Output Signal Valid (Output Delay) ADDR[8:31] BDIP BG4 BR5 CS[0:3] DATA[0:31] OE RD_WR TA TEA TS TSIZ[0:1] WE[0:3]/BE[0:3] tCOV -- 10.06/ 11.0 -- 7.56/ 8.5 -- 6.06/ 7.0 ns Output valid time selectable via SIU_ECCR[EBTS] bit: EBTS=0/EBTS=1 MPC5553 Microcontroller Data Sheet, Rev. 0 32 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 22. Bus Operation Timing1 (continued) 40 MHz (ext. bus)2 Min 7 Input Signal Valid to CLKOUT Posedge (Setup Time) ADDR[8:31] BB BG5 BR5 DATA[0:31] RD_WR TA TEA TS TSIZ[0:1] 8 CLKOUT Posedge to Input Signal Invalid (Hold Time) ADDR[8:31] BB BG5 BR5 DATA[0:31] RD_WR TA TEA TS TSIZ[0:1] 1 2 3 4 5 6 # Characteristic/Description Symbol 56 MHz (ext. bus)2 Min 7.0 Max -- 66 MHz (ext. bus)2 Min 5.0 Max -- Unit Notes Max -- tCIS 10.0 ns tCIH 1.0 -- 1.0 -- 1.0 -- ns EBI timing specified at VDD = 1.35V to 1.65V, VDDE = 1.6V to 3.6V (unless stated otherwise), VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH, and CL = 30pF with DSC = 0b10. The external bus is limited to half the speed of the internal bus. Refer to Fast Pad timing in Table 17 and Table 18 (different values for 1.8V vs 3.3V). Internal Arbitration External Arbitration The EBTS=0 timings are only valid/ tested at VDDE=2.25-3.6V, whereas EBTS=1 timings are valid/tested at 1.6-3.6V. Voh_f VDDE/2 CLKOUT Vol_f 3 2 2 4 1 Figure 11. CLKOUT Timing MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33 Electrical Characteristics CLKOUT VDDE/2 6 5 5 VDDE/2 OUTPUT BUS VDDE/2 6 5 5 OUTPUT SIGNAL VDDE/2 6 OUTPUT SIGNAL VDDE/2 Figure 12. Synchronous Output Timing MPC5553 Microcontroller Data Sheet, Rev. 0 34 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics CLKOUT VDDE/2 7 8 INPUT BUS VDDE/2 7 8 INPUT SIGNAL VDDE/2 Figure 13. Synchronous Input Timing MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35 Electrical Characteristics 3.13.5 Num 1 2 3 1 External Interrupt Timing (IRQ Pin) Table 23. External Interrupt Timing1 Characteristic Symbol tIPWL TIPWH 2 Min 3 3 6 Max -- -- -- Unit tCYC tCYC tCYC IRQ Pulse Width Low IRQ Pulse Width High IRQ Edge to Edge Time tICYC IRQ timing specified at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH, and CL = 200pF with SRC = 0b11. 2 Applies when IRQ pins are configured for rising edge or falling edge events, but not both. IRQ 1 3 2 Figure 14. External Interrupt Timing CLKOUT 4 IRQ Figure 15. External Interrupt Setup Timing MPC5553 Microcontroller Data Sheet, Rev. 0 36 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.13.6 Num 1 2 1 eTPU Timing Table 24. eTPU Timing1 Characteristic Symbol tICPW tOCPW Min 4 2 Max -- -- Unit tCYC tCYC eTPU Input Channel Pulse Width eTPU Output Channel Pulse Width eTPU timing specified at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH, and CL = 200pF with SRC = 0b11. 2 eTPU OUTPUT eTPU INPUT AND TCRCLK 1 Figure 16. eTPU Timing CLKOUT 4 eTPU OUTPUT 3 eTPU INPUT AND TCRCLK Figure 17. eTPU Input/Output Timing MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37 Electrical Characteristics 3.13.7 Num 1 2 1 eMIOS (MTS) Timing Table 25. MTS Timing1 Characteristic eMIOS (MTS) Input Pulse Width eMIOS (MTS) Output Pulse Width Symbol tMIPW tMOPW Min 4 1 Max -- -- Unit tCYC tCYC MTS timing specified at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH, and CL = 50pF with SRC = 0b11. 3.13.8 DSPI Timing Table 26. DSPI Timing1 80 MHz 112 MHz Min 17.9ns 15 14 -- -- -- Max 2.0ms -- -- -- 25 25 132 MHz Unit Min Max 2.9ms -- -- tSCK/2 + 2ns 25 25 Min 15.2ns 13 12 -- -- -- Max 1.7ms -- -- -- 25 25 -- ns ns ns ns ns 25ns 23 22 tSCK/2 -2ns -- -- Num 1 2 3 4 5 6 Characteristic SCK Cycle TIme2,3 PCS to SCK After SCK Delay4 Delay5 Symbol tSCK tCSC tASC tSDC tA tDIS SCK Duty Cycle Slave Access Time (SS active to SOUT driven) Slave SOUT Disable Time (SS inactive to SOUT High-Z or invalid) PCSx to PCSS time PCSS to PCSx time Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)6 Master (MTFE = 1, CPHA = 1) Data Hold Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)6 Master (MTFE = 1, CPHA = 1) 7 8 9 tPCSC tPASC tSUI 4 5 20 2 -4 20 -- -- -- -- -- -- -- -- -- -- 4 5 20 2 3 20 -4 7 14 -4 -- -- -- -- -- -- -- -- -- -- 4 5 20 2 6 20 -4 7 12 -4 -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns 10 tHI -4 7 21 -4 MPC5553 Microcontroller Data Sheet, Rev. 0 38 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 26. DSPI Timing1 (continued) 80 MHz Num 11 Characteristic Data Valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA=0) Master (MTFE = 1, CPHA=1) Data Hold Time for Outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Symbol Min tSUO -- -- -- -- tHO -5 5.5 8 -5 -- -- -- -- -5 5.5 4 -5 -- -- -- -- -5 5.5 3 -5 -- -- -- -- ns ns ns ns 5 25 18 5 -- -- -- -- 5 25 14 5 -- -- -- -- 5 25 13 5 ns ns ns ns Max Min Max Min Max 112 MHz 132 MHz Unit 12 1 2 3 4 5 6 DSPI timing specified at VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH, and CL = 50pF with SRC = 0b11. The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated based on two MPC55xx devices communicating over a DSPI link. The actual minimum SCK Cycle Time is limited by pad performance. The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK] The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC] This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10. 2 PCSx 4 SCK Output (CPOL=0) 4 1 3 SCK Output (CPOL=1) 9 SIN 10 Data 12 SOUT First Data Data Last Data 11 Last Data First Data Figure 18. DSPI Classic SPI Timing -- Master, CPHA = 0 MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 39 Electrical Characteristics PCSx SCK Output (CPOL=0) 10 SCK Output (CPOL=1) 9 SIN First Data 12 SOUT First Data Data Data Last Data 11 Last Data Figure 19. DSPI Classic SPI Timing -- Master, CPHA = 1 2 SS 1 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN 10 Data 12 Data 11 4 3 6 Last Data First Data Last Data Figure 20. DSPI Classic SPI Timing -- Slave, CPHA = 0 MPC5553 Microcontroller Data Sheet, Rev. 0 40 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics SS SCK Input (CPOL=0) SCK Input (CPOL=1) 5 SOUT 11 12 First Data 9 10 Data Last Data Data Last Data 6 SIN First Data Figure 21. DSPI Classic SPI Timing -- Slave, CPHA = 1 3 PCSx 4 2 SCK Output (CPOL=0) SCK Output (CPOL=1) 9 SIN First Data 12 SOUT First Data Data Data 11 Last Data Last Data 4 1 10 Figure 22. DSPI Modified Transfer Format Timing -- Master, CPHA = 0 MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 41 Electrical Characteristics PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) 9 SIN First Data Data 12 SOUT First Data Data 10 Last Data 11 Last Data Figure 23. DSPI Modified Transfer Format Timing -- Master, CPHA = 1 SS 2 1 3 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN First Data Data Data 11 12 Last Data 10 Last Data 6 4 Figure 24. DSPI Modified Transfer Format Timing -- Slave, CPHA =0 MPC5553 Microcontroller Data Sheet, Rev. 0 42 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics SS SCK Input (CPOL=0) SCK Input (CPOL=1) 5 SOUT 11 12 First Data 9 10 Data Last Data Data Last Data 6 SIN First Data Figure 25. DSPI Modified Transfer Format Timing -- Slave, CPHA =1 7 PCSS PCSx 8 Figure 26. DSPI PCS Strobe (PCSS) Timing MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 43 Electrical Characteristics 3.13.9 eQADC SSI Timing Table 27. EQADC SSI Timing Characteristics (pads at 3.3V or at 5.0V) 1 CLOAD = 25pF on all outputs. Pad drive strength set to maximum. Num 1 2 3 4 5 6 7 8 1 Rating FCK Frequency 2, 3 FCK Period (tFCK = 1/ fFCK) Clock (FCK) High Time Clock (FCK) Low Time SDS Lead/Lag Time SDO Lead/Lag Time EQADC Data Setup Time (Inputs) EQADC Data Hold Time (Inputs) Symbol fFCK tFCK tFCKHT tFCKLT tSDS_LL tSDO_LL tEQ_SU tEQ_HO Min 1/17 2 tSYS_CLK - 6.5 tSYS_CLK - 6.5 -7.5 -7.5 22 1 Typ -- -- -- -- -- -- -- -- Max 1/2 17 9* tSYS_CLK + 6.5 8* tSYS_CLK + 6.5 +7.5 +7.5 -- -- Unit fSYS_CLK tSYS_CLK ns ns ns ns ns ns SS timing specified at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH, and CL = 50pF with SRC = 0b11. 2 Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays. 3 FCK duty is not 50% when it is generated through the division of the system clock by an odd number. 2 3 FCK 5 SDS 25th 1st (MSB) 2nd 26th 4 4 6 SDO External Device Data Sample at FCK Falling Edge 8 7 SDI EQADC Data Sample at FCK Rising Edge 1st (MSB) 2nd 5 25th 26th Figure 27. EQADC SSI Timing MPC5553 Microcontroller Data Sheet, Rev. 0 44 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.14 Fast Ethernet AC Timing Specifications MII signals use TTL signal levels compatible with devices operating at 3.3 V. Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). 3.14.1 MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK) The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed 4x the RX_CLK frequency. Table 28 lists MII receive channel timings. Table 28. MII Receive Signal Timing Num 1 2 3 4 Characteristic RXD[3:0], RX_DV, RX_ER to RX_CLK setup RX_CLK to RXD[3:0], RX_DV, RX_ER hold RX_CLK pulse width high RX_CLK pulse width low Min 5 5 35% 35% Max -- -- 65% 65% Unit ns ns RX_CLK period RX_CLK period Figure 28 shows MII receive signal timings listed in Table 28. M3 RX_CLK (input) RXD[3:0] (inputs) RX_DV RX_ER M1 M2 M4 Figure 28. MII Receive Signal Timing Diagram MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 45 Electrical Characteristics 3.14.2 MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK) The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the TX_CLK frequency. The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs. Refer to the ethernet chapter of the device Reference Manual for details of this option and how to enable it. Table 29 lists MII transmit channel timings. Table 29. MII Transmit Signal Timing Num 5 6 7 8 Characteristic TX_CLK to TXD[3:0], TX_EN, TX_ER invalid TX_CLK to TXD[3:0], TX_EN, TX_ER valid TX_CLK pulse width high TX_CLK pulse width low Min 5 -- 35% 35% Max -- 25 65% 65% Unit ns ns TX_CLK period TX_CLK period Figure 29 shows MII transmit signal timings listed in Table 29. M7 TX_CLK (input) M5 TXD[3:0] (outputs) TX_EN TX_ER M6 M8 Figure 29. MII Transmit Signal Timing Diagram MPC5553 Microcontroller Data Sheet, Rev. 0 46 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.14.3 MII Async Inputs Signal Timing (CRS and COL) Table 30. MII Async Inputs Signal Timing Table 30 lists MII asynchronous inputs signal timing. Num 9 Characteristic CRS, COL minimum pulse width Min 1.5 Max -- Unit TX_CLK period Figure 30 shows MII asynchronous input timings listed in Table 30. CRS, COL M9 Figure 30. MII Async Inputs Timing Diagram 3.14.4 MII Serial Management Channel Timing (MDIO and MDC) Table 31 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Table 31. MII Serial Management Channel Timing Num 10 11 12 13 14 15 Characteristic MDC falling edge to MDIO output invalid (minimum propagation delay) MDC falling edge to MDIO output valid (max prop delay) MDIO (input) to MDC rising edge setup MDIO (input) to MDC rising edge hold MDC pulse width high MDC pulse width low Min 0 -- 10 0 40% 40% Max -- 25 -- -- 60% 60% Unit ns ns ns ns MDC period MDC period Figure 31 shows MII serial management channel timings listed in Table 31. MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 47 Electrical Characteristics M14 M15 MDC (output) M10 MDIO (output) M11 MDIO (input) M12 M13 Figure 31. MII Serial Management Channel Timing Diagram CLKOUT 5 5 RESET 6 6 RSTOUT Figure 32. Reset and Configuration Pin Timing MPC5553 Microcontroller Data Sheet, Rev. 0 48 Preliminary--Subject to Change Without Notice Freescale Semiconductor Mechanicals 4 4.1 4.1.1 Mechanicals Pinouts MPC5553 416 PBGA Pinout Figure 33, Figure 34, and Figure 35 show the pinout for the MPC5553 416 PBGA package. While the MPC5553 and the MPC5554/MPC5565/MPC5566 are pin-compatible, the MPC5553 ball map is shown here to highlight the balls that are not connected to any signal on the MCP5553 (the eTPUB[0:31] and TSIZ[0:1]). The alternate Ethernet signals that are multiplexed with the data bus are not shown for the MPC5553. NOTE Some pins have names that include functions that are not available on all family members. For example, ball R25 of the 416 BGA package is named `SINA,' but the MPC5553 does not have a DSPI_A module. In this case, the SINA pin can only be used for its alternate functions of GPIO94 or PCSC2. See the specific device reference manual for functions available on each device in the family. MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 49 Mechanicals 1 A B VSS VDD 2 VSTBY VSS VDD 3 AN37 AN36 VSS VDD 4 AN11 AN39 AN8 VSS VDD 5 VDDA1 AN19 AN17 AN38 6 AN16 AN20 VSSA1 AN9 7 AN1 AN0 AN21 AN10 8 AN5 AN4 AN3 AN18 9 VRH REF BYPC AN7 AN2 10 AN23 AN22 VRL AN6 11 AN27 AN26 AN25 AN24 12 AN28 AN31 AN30 AN29 13 AN35 AN32 AN33 14 VSSA0 VSSA0 VDDA0 15 AN15 AN14 AN13 16 ETRIG 1 ETRIG 0 NC_9 17 NC_1 NC_5 18 NC_2 NC_6 19 NC_3 NC_7 20 NC_4 21 GPIO 205 22 23 24 VDD MDO0 VSS VDDE7 TMS 25 VDD33 VSS VDDE7 TCK TDO EVTI GPIO 204 26 VSS A MDO11 MDO8 MDO4 MDO1 VSS VDDE7 NC_8 MDO10 MDO7 MDO6 MDO3 VDDE7 B VDD TDI TEST C D E C VDD33 D NC_10 NC_11 NC_12 MDO9 ETPUA ETPUA 30 31 AN34 VDDEH AN12 9 NC_13 NC_14 NC_15 NC_16 MDO5 MDO2 VDDEH 8 ETPUA ETPUA VDDEH E 28 29 1 F G ETPUA ETPUA ETPUA VDDEH 24 27 26 1 ETPUA ETPUA ETPUA ETPUA 23 22 25 21 MSEO0 JCOMP MSEO1 MCKO EVTO F NC_17 G ETPUA ETPUA ETPUA ETPUA H 20 19 18 17 J K ETPUA ETPUA ETPUA ETPUA 16 15 14 13 ETPUA ETPUA ETPUA ETPUA 12 11 10 9 VSS VSS Version 2.1 - 13 July 2004 RDY GPIO 203 NC_18 NC_19 H VDDEH NC_20 NC_21 NC_22 J 6 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS NC_23 NC_24 NC_25 NC_26 K NC_27 NC_28 NC_29 NC_30 L NC_31 NC_32 NC_33 SINB M ETPUA ETPUA ETPUA ETPUA L 8 7 6 5 M N P R ETPUA ETPUA ETPUA ETPUA 4 3 2 1 BDIP CS3 WE3 TEA CS2 WE2 ETPUA TCRCLK 0 A CS1 WE1 CS0 WE0 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS SOUTB PCSB3 PCSB0 PCSB1 N PCSA3 PCSB4 SCKB PCSB2 P PCSB5 SOUTA SINA SCKA R VPP T T VDDE2 NC_34 RD_WR VDDE2 ADDR U NC_35 16 V W Y ADDR 18 ADDR 20 ADDR 22 ADDR 17 ADDR 19 ADDR 21 ADDR 23 ADDR 25 ADDR 27 ADDR 30 VSS VDD 2 TA TS ADDR 9 VDD33 ADDR 8 ADDR 10 VDDE2 VDDE2 VDDE2 VDDE2 PCSA1 PCSA0 PCSA2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 PCSA4 TXDA PCSA5 VFLASH U CNTXC RXDA RSTOUT RST CFG V ADDR VDDE2 11 ADDR 13 ADDR 15 ADDR 31 VSS VDD DATA 16 3 ADDR 12 ADDR 14 VSS VDD DATA 17 DATA 18 4 VDD DATA 24 DATA 19 VDDE2 5 DATA 26 DATA 25 DATA 21 DATA 20 6 DATA 28 DATA 27 DATA 23 DATA 22 7 VDDE2 DATA 29 DATA 0 GPIO 206 8 Note: NC_X NC_36 No connects (x = 1 to 38) NC_37 RXDB CNRXC TXDB RESET W WKP CFG BOOT CFG1 VRC VSS VSS SYN Y ADDR AA 24 AB VDDE2 ADDR AC 26 AD AE AF ADDR 28 ADDR 29 VSS 1 No connect. AC22 & AD23 reserved VDDEH PLL 6 CFG1 VDD VRC CTL VDD VSS BOOT EXTAL AA CFG0 PLL CFG0 VRC33 VDD XTAL VDD SYN AB AC DATA 30 VDD33 DATA 2 DATA 1 9 DATA 31 GPIO 207 DATA 4 DATA 3 10 DATA 8 DATA 9 DATA 6 VDDE2 11 DATA 10 DATA 11 OE DATA 5 12 VDDE2 DATA 13 BR DATA 7 13 DATA 12 DATA 15 BG DATA 14 EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 NC_36 2 8 12 21 4 VSS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 NC_37 6 10 3 15 17 22 VDD33 AD VDD VSS 26 AE AF EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 5 9 1 13 16 19 23 ENG CLK 25 NC_38 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 4 7 0 11 14 18 20 14 15 16 17 18 19 20 21 22 23 24 Figure 33. MPC5553 416 Package MPC5553 Microcontroller Data Sheet, Rev. 0 50 Preliminary--Subject to Change Without Notice Freescale Semiconductor Mechanicals 1 A B VSS VDD 2 VSTBY VSS VDD 3 AN37 AN36 VSS VDD 4 AN11 AN39 AN8 VSS VDD 5 VDDA1 AN19 AN17 AN38 6 AN16 AN20 VSSA1 AN9 7 AN1 AN0 AN21 AN10 8 AN5 AN4 AN3 AN18 9 VRH REF BYPC AN7 AN2 10 AN23 AN22 VRL AN6 11 AN27 AN26 AN25 AN24 12 AN28 AN31 AN30 AN29 13 AN35 AN32 AN33 AN34 C VDD33 D E F G H J K L M N P R ETPUA ETPUA 30 31 ETPUA ETPUA VDDEH 28 29 1 ETPUA ETPUA ETPUA VDDEH 24 27 26 1 ETPUA ETPUA ETPUA ETPUA 23 22 25 21 ETPUA ETPUA ETPUA ETPUA 20 19 18 17 ETPUA ETPUA ETPUA ETPUA 16 15 14 13 ETPUA ETPUA ETPUA ETPUA 12 11 10 9 ETPUA ETPUA ETPUA ETPUA 8 7 6 5 ETPUA ETPUA ETPUA ETPUA 4 3 2 1 BDIP CS3 WE3 TEA CS2 WE2 ETPUA TCRCLK 0 A CS1 WE1 CS0 WE0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Version 2.1 - 13 July 2004 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS T VDDE2 NC_34 RD_WR VDDE2 U V W Y ADDR NC_35 16 ADDR 18 ADDR 20 ADDR 22 ADDR 17 ADDR 19 ADDR 21 ADDR 23 ADDR 25 ADDR 27 ADDR 30 VSS VDD 2 TA TS ADDR 9 VDD33 ADDR 8 ADDR 10 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 Note: NC_X NC_36 No connects (x = 1 to 38) NC_37 ADDR VDDE2 11 ADDR 13 ADDR 15 ADDR 31 VSS VDD DATA 16 3 ADDR 12 ADDR 14 VSS VDD DATA 17 DATA 18 4 VDD DATA 24 DATA 19 VDDE2 5 No connect. AC22 & AD23 reserved ADDR AA 24 AB VDDE2 AC AD AE AF ADDR 26 ADDR 28 ADDR 29 VSS 1 DATA 26 DATA 25 DATA 21 DATA 20 6 DATA 28 DATA 27 DATA 23 DATA 22 7 VDDE2 DATA 30 DATA 29 DATA 0 GPIO 206 8 VDD33 DATA 2 DATA 1 9 DATA 31 GPIO 207 DATA 4 DATA 3 10 DATA 8 DATA 9 DATA 6 DATA 10 DATA 11 OE VDDE2 DATA 13 BR DATA 7 13 VDDE2 DATA 5 11 12 Figure 34. MPC5553 416 Package, Left Side MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 51 Mechanicals 14 VSSA0 VSSA0 VDDA0 15 AN15 AN14 AN13 16 ETRIG 1 ETRIG 0 NC_9 17 NC_1 NC_5 18 NC_2 NC_6 19 NC_3 NC_7 20 NC_4 21 22 23 24 VDD MDO0 VSS VDDE7 TMS 25 VDD33 VSS VDDE7 TCK TDO EVTI GPIO 204 26 VSS A GPIO MDO11 MDO8 205 MDO4 MDO1 VSS VDDE7 NC_8 MDO10 MDO7 MDO6 MDO3 VDDE7 B VDD TDI TEST EVTO C D E F NC_10 NC_11 NC_12 MDO9 VDDEH AN12 9 NC_13 NC_14 NC_15 NC_16 MDO5 MDO2 VDDEH 8 MSEO0 JCOMP MSEO1 MCKO RDY GPIO 203 NC_17 G NC_18 NC_19 H VDDEH NC_20 NC_21 NC_22 J 6 VDDE7 VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VSS VSS VSS VSS NC_23 NC_24 NC_25 NC_26 K NC_27 NC_28 NC_29 NC_30 L NC_31 NC_32 NC_33 SINB M SOUTB PCSB3 PCSB0 PCSB1 N PCSA3 PCSB4 SCKB PCSB2 P PCSB5 SOUTA SINA SCKA R VPP T VDDE2 VDDE2 VDDE2 VDDE2 PCSA1 PCSA0 PCSA2 PCSA4 TXDA PCSA5 VFLASH U CNTXC RXDA RSTOUT RST CFG V RXDB CNRXC TXDB RESET W WKP CFG BOOT CFG1 VRC VSS VSS SYN Y VDDEH PLL CFG1 6 VDD DATA 12 DATA 15 BG DATA 14 EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 NC_36 2 8 12 21 4 VSS VRC CTL VDD VSS BOOT EXTAL AA CFG0 PLL CFG0 VRC33 VDD XTAL VDD SYN AB AC EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 NC_37 3 6 10 15 17 22 VDD33 AD VDD VSS 26 AE AF EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 1 5 9 13 16 19 23 ENG CLK 25 NC_38 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 0 4 7 11 14 18 20 14 15 16 17 18 19 20 21 22 23 24 Figure 35. MPC5553 416 Package, Right Side MPC5553 Microcontroller Data Sheet, Rev. 0 52 Preliminary--Subject to Change Without Notice Freescale Semiconductor Mechanicals 4.1.2 1 A VSS 2 VDD VSS MPC5553 324 PBGA Pinout 3 VSTBY VDD VSS 4 AN37 AN36 VDD VSS 5 AN11 AN39 AN8 VDD 6 7 8 AN1 AN0 AN21 AN10 9 AN5 AN4 AN3 AN18 10 VRH REF BYPC AN7 AN2 11 VRL AN23 AN22 AN6 12 AN27 AN26 AN25 AN24 13 AN28 AN31 AN30 AN29 14 AN35 AN32 AN33 15 VSSA0 VSSA0 VDDA0 16 17 18 19 20 VDD MDO0 VSS VDDE7 TMS 21 VDD33 VSS VDDE7 TCK TDO EVTI 22 VSS A Figure 36 is a pinout for the MPC5553 324 PBGA package. VDDA1 VSSA1 AN19 AN17 AN38 AN16 AN20 AN9 AN12 MDO11 MDO10 MDO8 AN13 AN14 MDO9 MDO5 MDO6 MDO7 MDO2 MDO3 MDO4 MDO1 VSS VDDE7 B VDD33 C D VDDE7 B VDD TDI TEST EVTO C D E F ETPUA ETPUA 30 31 ETPUA ETPUA ETPUA 28 29 26 AN34 VDDEH AN15 9 ETPUA ETPUA ETPUA ETPUA E 24 27 25 21 ETPUA ETPUA ETPUA ETPUA F 23 22 17 18 ETPUA ETPUA ETPUA ETPUA G 20 19 14 13 ETPUA ETPUA ETPUA VDDEH H 16 15 10 1 ETPUA ETPUA ETPUA ETPUA J 6 12 11 9 ETPUA ETPUA ETPUA ETPUA K 8 7 2 5 ETPUA ETPUA ETPUA ETPUA L 4 3 0 1 M N P R TCRCLK BDIP A CS3 ADDR 16 ADDR 18 CS2 CS1 WE1 CS0 WE0 VDDE7 JCOMP Version 2.2p - 13 July 2004 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VSS VSS VSS VSS VSS RDY MCKO MSEO0 MSEO1 G GPIO 204 SINB H VDDEH GPIO 10 203 SOUTB PCSB3 PCSB0 PCSB1 J PCSA3 PCSB4 SCKB PCSB2 K PCSB5 SOUTA SINA SCKA L VPP M VDDE2 VDDE2 VSS VSS VSS VSS PCSA1 PCSA0 PCSA2 PCSA4 TXDA PCSA5 VFLASH N CNTXC RXDA RSTOUT WKP CFG RST CFG P ADDR RD_WR VDD33 17 ADDR VDDE2 19 ADDR 21 ADDR 23 ADDR 25 ADDR 12 ADDR 13 ADDR 15 TA TS ADDR 14 ADDR 31 VSS VDD VDD CNRXC TXDB RESET R BOOT CFG1 VRC VSS VSS SYN T ADDR T 20 ADDR U 22 V ADDR 24 Note: NC No connect. Reserved (W18 & Y19 are shorted to each other) RXDB VDDEH PLL 6 CFG1 VDD VRC CTL VDD VSS BOOT EXTAL U CFG0 PLL CFG0 VRC33 VDD XTAL VDD SYN V W ADDR ADDR W VDDE2 26 30 ADDR Y 28 ADDR AA 29 AB VSS 1 ADDR 27 VSS VDD 2 VSS VDD VDDE2 VDD33 VDDE2 DATA 11 DATA 9 GPIO 206 DATA 4 7 DATA 10 DATA 5 DATA 6 8 GPIO 207 DATA 7 OE 9 DATA 12 DATA 13 DATA 14 DATA 15 EMIOS EMIOS VDDEH EMIOS EMIOS VDDE5 21 2 4 12 8 NC VSS NC VDDE2 DATA 8 VDDE2 DATA 3 6 EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 22 6 10 15 17 VDD33 Y VDD VSS 22 AA AB VDDE2 DATA 1 DATA 2 5 VDDE2 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 16 19 23 3 5 9 13 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 14 18 20 0 1 4 7 11 10 11 12 13 14 15 16 17 18 19 20 ENG CLK 21 DATA VDDE2 0 3 4 Figure 36. MPC5553 324 Package MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 53 Mechanicals 4.1.3 MPC5553 208 MAP BGA Pinout NOTE VDDEH10 and VDDEH6 are connected internally on the 208-ball package and are listed as VDDEH6. Figure 37 is a pinout for the MPC5553 208 MAP BGA package. 1 A B VSS VDD 2 AN9 VSS VDD AN39 3 AN11 AN38 VSS VDD AN37 4 5 6 AN1 AN4 AN16 AN2 7 AN5 REF BYPC AN3 AN6 8 VRH AN22 AN7 AN24 9 VRL AN25 AN23 AN30 10 AN27 AN28 AN32 AN31 11 VSSA0 VDDA0 AN33 12 AN12 AN13 AN14 13 MDO2 MDO3 AN15 VSS VDDE7 14 15 16 VSS VDD TCK TEST A B C D VDDA1 VSSA1 AN21 AN17 VSS VDD AN36 AN0 AN34 AN18 MDO0 VDD33 MDO1 VSS TMS TDI TDO VSS MSEO0 EVTO EVTI C VSTBY D VDD33 E F G H J K L M N P R T AN35 VDDEH 9 ETPUA ETPUA 30 31 MSEO1 E ETPUA ETPUA ETPUA 28 29 26 8 June 2005p VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDEH 6 MCKO JCOMP F SINB PCSB0 G ETPUA ETPUA ETPUA ETPUA 24 27 25 21 ETPUA ETPUA ETPUA ETPUA 23 22 17 18 ETPUA ETPUA ETPUA ETPUA 14 20 19 13 ETPUA ETPUA ETPUA VDDEH 16 15 7 1 ETPUA ETPUA ETPUA TCRCLK 12 11 6 A ETPUA ETPUA ETPUA ETPUA 10 9 1 5 ETPUA ETPUA ETPUA 8 4 0 ETPUA ETPUA 3 2 CS0 VSS 1 VSS VDD 2 VSS VDD OE 3 VSS VDD GPIO 206 SOUTB PCSB3 PCSA3 PCSB4 PCSB2 PCSB1 H PCSB5 TXDA PCSA2 SCKB J CNTXC RXDA RSTOUT TXDB CNRXC WKP CFG BOOT CFG1 PLL CFG1 VRC33 VSS VDD 15 VPP K RESET L VSS SYN M Note: VDD GPIO 207 CS0 No connect. R1 reserved for CS0 RXDB VSS VDD PLL CFG0 VRC CTL VSS VDD ENG CLK 14 VDD33 EMIOS EMIOS VDDEH EMIOS EMIOS VDD33 12 4 2 10 21 VDDE2 EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA 16 17 6 8 22 EXTAL N XTAL VDD SYN VSS 16 P R T EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA CNRXB 14 19 23 4 3 9 11 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB VDDE5 15 18 20 0 1 5 7 13 4 5 6 7 8 9 10 11 12 13 Figure 37. MPC5553 208 Package MPC5553 Microcontroller Data Sheet, Rev. 0 54 Preliminary--Subject to Change Without Notice Freescale Semiconductor Mechanicals 4.2 4.2.1 Package Dimensions MPC5553 416-Pin Package Figure 38 is a package drawing of the MPC5553 416 pin TEPBGA package. Figure 38. MPC5553 416 TEPBGA Package MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 55 Mechanicals 4.2.2 MPC5553 324-Pin Package Figure 39 is a package drawing of the MPC5553 324-pin TEPBGA package. Figure 39. MPC5553 324 TEPBGA Package MPC5553 Microcontroller Data Sheet, Rev. 0 56 Preliminary--Subject to Change Without Notice Freescale Semiconductor Mechanicals 4.2.3 MPC5553 208-Pin Package Figure 40 is a package drawing of the MPC5553 208-pin MAP BGA package. Figure 40. MPC5553 208 MAP BGA Package MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 57 Revision History 5 Revision History Table 32. Revision History Revision Rev. 0 Location(s) Substantive Change(s) This is the first released version of this document. Table 32 provides a revision history of this document. MPC5553 Microcontroller Data Sheet, Rev. 0 58 Preliminary--Subject to Change Without Notice Freescale Semiconductor THIS PAGE IS INTENTIONALLY BLANK MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 59 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: MPC5553 Rev. 0 06/2006 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. 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Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. 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